Section 9. Watchdog Timer WDT. Section Power- Saving Features. Input Capture. Dual Comparator Module. Comparator Voltage Reference Module. High-Level Device Integration. Programming and Diagnostics. Output Compare with Dedicated Timer. Reset with Programmable Brown-out Reset. Scalable Comparator Module. Motor Control PWM. Comparator with Blanking. Power-Saving Features with Vbat. Operational Amplifier Op Amp. Section 5. Flash Programming. Section 8. Reset old? The Program Memory and Data Memory have separate buses so.
The Data Memory , Table and Table Reset Vector h Interrupt Vector h h Program Memory , appreciate your assistance in making this a better document. Key Reference Manual Features Operating. Abstract: No abstract text available Text:. A block diagram of the device is shown in Figure OK, Thanks We use Cookies to give you best experience on our website. Migration from Baseline to Midrange Devices. On-Line Support Reader Response Identification System. To obtain the most up-to-date version of this data sheet, please check our Worldwide Web site at:.
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FAX: We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure that this document is correct. However, we realize that we may have missed a few things. The Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules.
A block diagram of the device is shown in Figure The program memory contains 1K words, which translates to instructions, since each bit program memory word is the same width as each device instruction. The data memory RAM contains 68 bytes. Some pins are multiplexed with other device functions. These functions include:. Table details the pinout of the device with descriptions and details for each pin.
These are the program memory and the data memory. Each block has its own bus, so that access to each block can occur during the same oscillator cycle. The SFRs used to control the peripheral modules are described in the section discussing each individual peripheral module.
This memory is not directly mapped into the data memory, but is indirectly mapped. Accessing a location above the physically implemented address will cause a wraparound.
For example, for locations 20h, h, h, C20h, h, h, h, and 1C20h will be the same instruction. User Memory Space. The data memory is partitioned into two areas. The SFRs control the operation of the device. Portions of data memory are banked. The banked areas of the SFR are for the registers that control the peripheral functions. Banking requires the use of control bits for bank selection.
Figure shows the data memory map organization. Indirect addressing uses the present value of the RP0 bit for access into the banked areas of data memory. Data memory is partitioned into two banks which contain the general purpose registers and the special function registers.
Setting the RP0 bit selects Bank 1. Each Bank extends up to 7Fh bytes. The GPR addresses in bank 1 are mapped to addresses in bank 0. These registers are static RAM. Those associated with the core functions are described in this section. The upper byte of the program counter is not directly accessible. The contents. These bits are set or cleared according to device logic. Furthermore, the TO and PD bits are not writable. Note 2: The C and DC bits operate as a borrow and digit borrow out bit, respectively, in subtraction.
Each bank is bytes. RP1 should be maintained clear. Note: For borrow the polarity is reversed. The PC is 13 bits wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called the PCH register. The stack allows a combination of up to 8 program calls and interrupts to occur. The stack contains the return address from this branch in program execution.
Midrange devices have an 8 level deep x bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The tenth push overwrites the second push and so on. The INDF register is not a physical register. This is indirect addressing.
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